module MODULE_DSRAM
#(AWIDTH=32)
(
	input										clk_i,
	input 									rst_i,

	input	[AWIDTH-1:0]			araddr_i,
	input										arvalid_i,
	output									arready_o,

	output		[`WIDTH-1:0]	rdata_o,
	output		[1:0]					rresp_o, //not handled yet just out 2'b0
	output									rvalid_o,
	input										rready_i,

	input			[AWIDTH-1:0]	awaddr_i,
	input										awvalid_i,
	output									awready_o,

	input			[`WIDTH-1:0]	wdata_i,
	input			[7:0]					wstrb_i,
	input										wvalid_i,
	output									wready_o,

	output		[1:0]					bresp_o,//not finished 
	output									bvalid_o,//not...
	input										bready_i//not...
);

	wire			[`WIDTH-1:0]	data_r;
	wire										data_r_valid; 
	wire		[AWIDTH-1:0]	addr_r;
	wire									addr_r_valid;
	wire	 	[`WIDTH-1:0]	data_w;
	wire		[7:0]	data_w_mask;
	wire									data_w_valid;
	wire		[AWIDTH-1:0]	addr_w;
MODULE_AXI_Lite_S  axi_lite_s2(
	.clk_i									(clk_i),
	.rst_i									(rst_i),
	.data_r_i								(data_r),
	.data_r_valid_i					(data_r_valid),
	.addr_r_o								(addr_r),
	.addr_r_valid_o					(addr_r_valid),
	.data_w_o								(data_w),
	.data_w_mask_o					(data_w_mask),
	.data_w_valid_o					(data_w_valid),
	.addr_w_o								(addr_w),
	.data_w_end_i						(w_end),

	.araddr_i								(araddr_i),
	.arvalid_i							(arvalid_i),
	.arready_o							(arready_o),
	.rdata_o								(rdata_o),
	.rresp_o								(rresp_o), 
	.rvalid_o								(rvalid_o),
	.rready_i								(rready_i),
	.awaddr_i								(awaddr_i),
	.awvalid_i							(awvalid_i),
	.awready_o							(awready_o),
	.wdata_i								(wdata_i),
	.wstrb_i								(wstrb_i),
	.wvalid_i								(wvalid_i),
	.wready_o								(wready_o),
	.bresp_o								(bresp_o),
	.bvalid_o								(bvalid_o),
	.bready_i								(bready_i)
);

//read 
wire [7:0]	rvalid;
wire [`WIDTH-1:0]	rdata_r;
import "DPI-C" function void pmem_read_hard(input longint raddr,output longint rdata,output byte valid,input byte read_en);
always @(*) begin
				pmem_read_hard({{(`WIDTH-AWIDTH){1'b0}},addr_r[AWIDTH-1:0]},rdata_r[`WIDTH-1:0],rvalid[7:0],{7'b0,&addr_r_valid});
end
	//delay one cycle for read
Reg#(1,0) valid_r(clk_i,rst_i,rvalid[0],data_r_valid,1);
Reg#(`WIDTH,0) rdata_reg(clk_i,rst_i,rdata_r[`WIDTH-1:0],data_r[`WIDTH-1:0],rvalid[0]);


//write
wire [7:0] wvalid;
wire wvalid_1;
wire wvalid_2;
wire [`WIDTH-1:0] wdata_r;
wire [7:0] wdata_mask_r;
wire w_end;
wire [7:0] w_end1;
import "DPI-C" function void pmem_write_hard(input longint waddr, input longint wdata, input byte wmask,output byte w_end,input byte write_en);
	//delay one cycle for data and valid to sim the delay
Reg#(1,0) valid_w(clk_i,rst_i,data_w_valid,wvalid_1,1);
Reg#(1,0) valid_w1(clk_i,rst_i,wvalid_1,wvalid_2,1);
assign wvalid = {7'b0,wvalid_1&~wvalid_2};
Reg#(1,0) end_reg(clk_i,rst_i,wvalid[0],w_end,1);
Reg#(`WIDTH,0) wdata_reg(clk_i,rst_i,data_w[`WIDTH-1:0],wdata_r[`WIDTH-1:0],data_w_valid);
Reg#(8,0) wdata_mask_reg(clk_i,rst_i,data_w_mask[7:0],wdata_mask_r[7:0],data_w_valid);
always @(*) begin
		pmem_write_hard({{(`WIDTH-AWIDTH){1'b0}},addr_w[AWIDTH-1:0]},wdata_r[`WIDTH-1:0],wdata_mask_r[7:0],w_end1[7:0],wvalid);
end
endmodule
